Programmable devices are a class of general-purpose integrated circuits that can be configured for a wide variety of applications. Such programmable devices have two basic versions, mask programmable devices, which are programmed only by a manufacturer, and field programmable devices, which are programmable by the end user. In addition, programmable devices can be further categorized as programmable memory devices or programmable logic devices. Programmable memory devices include programmable read only memory (PROM), erasable programmable read only memory (EPROM) and electronically erasable programmable read only memory (EEPROM). Programmable logic devices include programmable logic array (PLA) devices, programmable array logic (PAL) devices, erasable programmable logic devices (EPLD) devices, and programmable gate arrays (PISA).
As chip capacity continues to increase significantly, the use of field programmable gate arrays (FPGAs) is quickly replacing the use of application specific integrated circuits (ASICs). An ASIC is a specialized integrated circuit that is designed for a particular application and can be implemented as a specialized microprocessor. Notably, a FPGA is a programmable logic device (PLD) that has an extremely high density of electronic gates as compared to an ASIC. This high gate density has contributed immensely to the popularity of FPGAs. Notably, FPGAs can be designed using a variety of architectures that can include user configurable input/output blocks (IOBs), and programmable logic blocks having configurable interconnects and switching capability.
The advancement of computer chip technology has also resulted in the development of embedded processors and controllers. An embedded processor or controller can be a microprocessor or microcontroller circuitry that has been integrated into an electronic device as opposed to being built as a standalone module or “plugin card.” Advancement of FPGA technology has led to the development of FPGA-based system-on-chips (SoC) including FPGA-based embedded processor system-on-chips. A SoC is a fully functional product having its electronic circuitry contained on a single chip. While a microprocessor chip requires ancillary hardware electronic components to process instructions, a SoC would include all required ancillary electronics. For example, a SoC for a cellular telephone can include a microprocessor, encoder, decoder, digital signal processor (DSP), RAM and ROM. It should be understood within contemplation of the present invention that an FPGA-Based SoC does not necessarily include a microprocessor or microcontroller. For example, a SoC for a cellular telephone could also include an encoder, decoder, digital signal processor (DSP), RAM and ROM that rely on an external microprocessor. It should also be understood herein that “FPGA-based embedded processor SoCs” are a specific subset of FPGA-based SoCs that would include their own processors.
In order for device manufacturers to develop FPGA-based embedded processor SoCs or FPGA-based SoCs, it is necessary for them to acquire intellectual property rights for system components and/or related technologies that are utilized to create the FPGA-based SoCs. These system components and/or technologies are called cores or Intellectual Property (IP) cores. An electronic file containing system component information can typically be used to represent the core. A device manufacturer will generally acquire several cores that are integrated to fabricate the SoC.
Notwithstanding advantages provided by using FPGA-based SoCs, the development of these SoCs can be very challenging. Although a vast proportion of cores are commercially available, a significantly greater proportion of cores are proprietary. Proprietary cores can be called customer specific cores. Commercially available cores can typically include standardized interfaces, which can provide interconnectivity between system components from various vendors. Customer specific cores can typically include proprietary interfaces that do not readily facilitate interconnectivity between system components from other vendors. For example, customer specific cores can be written in proprietary languages, which are completely different from standardized languages. Since customer specific cores do not readily facilitate interconnectivity with other vendor's system components, integrating customer specific cores during customization of an FPGA-based SoC can be time consuming. This resulted in increased development cost and greater time-to-market. Integration of the cores can include modeling, simulating, and debugging the integrated cores in an operating environment. Simulation and modeling can be a daunting task since it can take hours if not days to simulate a few milliseconds of real time operation.
Traditional ASIC-based embedded processor SoCs have utilized fixed ASIC solutions and standard cell technology, which have very limited customization capability. Although attempts have been made to provide a fair level of choices for customization, there is minimal choice of system components or peripherals required for customizing the ASIC-based embedded processor SoC. This has resulted in a limited flexibility in matching ASIC-based embedded processor SoC solutions to system requirements. For example, the availability of system resources can dictate whether a protocol stack is hardware-based or software-based. The availability of sufficient processing power can indicate that it might be advantageous to utilize a software-based protocol stack. Similarly, the availability of sufficient FPGA resources or a high performance requirement can implicate the use of a hardware-based protocol stack.
Notably, ASIC-based embedded processor SoC solutions have high up-front development costs and high non-recurring engineering costs. A major reason for the high up-front development and non-recurring engineering costs includes deep-sub-micron issues that complicate ASIC-based embedded processor SoC solutions. These sub-micron issues can result in multiple design and system verification iterations, which not only increase development cost, but also significantly increase product cost. Moreover, the lack of IP, for example software IP, has further limited the scope of customization. Importantly, exponential rising costs and the difficulty associated with completing complex designs, often make customization unrealistic for designs that typically have budgetary and time-to-market constraints.
During development of FPGA-based embedded processor SoCs, the ability to select from a choice of system components, and to configure various software and hardware parameters can result in wide variations in system performance and system cost. Such variations can result in a significant departure from system requirements and specifications. Consequently, a method and system for optimizing resource selection and allocation during customization of FPGA-based embedded processor SoCs would be advantageous.